1. Field
The present teachings relate to amplifier biasing. In particular, the present teachings relate to amplifiers and related methods and devices.
2. Description of Related Art
In low voltage (<4 volt) semiconductor technology such as silicon on insulator (SOI), typical transistors can only withstand a limited voltage across the drain-source terminals before experiencing reliability issues. A typical maximum voltage is around 4 volts for an SOI technology with a minimum feature size of 0.5 um for the gate electrode and decreases as the minimum feature size is decreased. This limitation poses a challenge when designing circuitry such as an operational amplifier intended to operate at a much higher power supply voltage (such as 10 V or greater). Typical applications using high voltage amplifiers, involve generating output common mode voltages approaching the limits of the positive and negative supply. In a careful design, the constituent transistors of such amplifiers do not experience excessive voltage across their drain and source terminal as to incur reliability issues. Moreover, a high voltage operational amplifier is designed to deliver a wide range of input common mode levels approaching the positive and negative supply.
FIG. 1 shows an output stage (100) of a folded cascode topology high voltage operational amplifier. The folded cascode refers to the folding of N-channel cascode active loads of a differential pair and then changing the MOSFETs to P-channel. The amplifier output stage (100) is designed to provide an output voltage which approaches a positive and negative supply, VDD and VSS in the Figure, by using a series of stacked transistors VCascode_x (x ranging from 1 to 24 in the example of the Figure) of complementary devices (N-channel FETs and P-channel FETs in the example of the Figure) in a push-pull fashion. The push-pull comes from the ability to drive either a positive or negative current into a load by using a complementary pair of transistors (N-channel and P-channel). Transistors (110), (111), (112), and (113) are used to set a bias current through the output stage (100) transistors via gate bias node voltage (120) and (130).
Referring to FIG. 1, a number of transistor devices needed in series depends on a total voltage that the operational amplifier output stage (100) is able to withstand. For a given stress voltage level supported by a technology, a higher voltage supply implies the use of a higher number of transistors stacked.
Further referring to FIG. 1, it is desirable that the series stacked cascode transistors VCascode_x be biased in a way to ensure that the total voltage across the stack is evenly distributed among the transistors VCascode_x. In this way, it is ensured that each transistor is not over stressed with a voltage between drain and source terminals which exceeds the limits of the fabrication technology.